Читать книгу Digital System Design using FSMs - Peter D. Minns - Страница 27

A completed state diagram with unit distance patterns for flip‐flops is shown in Figure 1.13.

Figure 1.13 State diagram for single‐pulse generator with memory and dummy state.

Note that the added state has the unique name of s3 and the unique flip‐flop assignment of A = 0 and B = 1.

Also note that s2 uses the A and B values of A = 1 and B = 1. This provides the required unit distance coding. It also has the output P = 0, as it would in state s0 (the state it is going to go to when s = 0).

In this design the addition of the extra state has not added any more flip‐flops to the design since two flip‐flops can have a maximum of 2² = 4 states (remember Frames 1.2 and 1.3).

The addition of this extra state is usually called a dummy state.

Look carefully at the state diagram in Frame 1.13 and satisfy yourself that the state diagram is doing the same thing as the one in Frame 1.11. If you cannot see this, consider reading Frames 1.11–1.13 again.

Now let us add an additional input called r to our state diagram.

Input r is to be added so that if r = 1 the FSM will continue to pulse output P (on and off) until r is made 0. At this point the FSM will return to state s0 but only if input s = 0.

Draw the block diagram for the FSM.

Draw the state diagram for this modified FSM.

Take your time and think about what you are doing.

Turn to Frame 1.14 when you have completed this task.