Читать книгу Digital System Design using FSMs - Peter D. Minns - Страница 30

The outputs in our FSM are seen to be dependent upon the SSVs or flip‐flops internal to the FSM. If you look back to Frame 1.5 you will see that Moore FSM outputs are dependent upon the flip‐flop outputs only. The output decoding logic in our P pulse example is:

That is it consists of an AND gate and a NAND gate. This means that a single P pulse is a Moore FSM.

How could we make our single‐pulse design into a Mealy FSM?

One way would be to make the output P depend on the FSM being in state s1 (A/B), but we could say that the output was to be the width of a single logic 0 of the clock pulse.

How would we modify our state diagram to do this?

Try doing this, and then turn to Frame 1.16 to find out if you got it right.