Читать книгу Digital System Design using FSMs - Peter D. Minns - Страница 32

The solution to this problem is to use the basic arrangement of the single‐pulse state diagram and insert more states to generate the required 101 pattern (Figure 1.19).

Figure 1.19 Development of a 101 pattern generator sequence.

It will develop state by state so you can see how it is done.

Note that we must leave state s3 on a clock pulse so that P = 1 for the duration of a single clock pulse only.

The final state required is to monitor for the input s = 0 condition.

This state should return the FSM back to state s0.

1 Complete the FSM state diagram then turn to Frame 1.18.