Читать книгу Digital System Design using FSMs - Peter D. Minns - Страница 33

Frame 1.18

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The completed state diagram is shown in Figure 1.20.


Figure 1.20 Complete state diagram for the 101 pattern generator.

The Boolean equation for P in this diagram is P = s1 + s3. However, we could make the P output a Mealy output that is only equal to 1 when in states s1 and s3, and only if the clock pulse is equal to 1.

Then, P = s1·clk + s3·clk since P must be high in both states s1 and s3, but only when the clock input is high.

Try writing an account of how this FSM works in your own words. If you get stuck, just re‐read Frames 1.16and 1.17again to refresh your memory.

Now try modifying the state diagram to make it produce a 101 sequence of clock pulses (in the same manner as shown in Frames 1.17and 1.18).

Also, arrange for the P output pulse in state s3 to be conditional on a new input called x. If x = 0, the FSM should produce the output sequence 100 at P. If x = 1, the output sequence at P should be 101.

The reader may have noticed that the state diagram does not need to use slings. This is because slings are not really necessary with modern state diagrams. In fact, they are really only included for cosmetic reasons, to improve the readability of the design. From now on, only use slings where they improve the readability of the state diagram.

1 When you have done this, draw your state diagram and then turn to Frame 1.19.

Digital System Design using FSMs

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